(a) Field of the Invention
The present invention relates to a PDP (plasma display panel) driving method and a plasma display device.
(b) Description of the Related Art
A PDP is a flat display for showing characters or images using plasma generated by gas discharge. PDPs can include pixels numbering more than several million in a matrix format, in which the number of pixels are determined by the size of the PDP. Referring to FIGS. 1 and 2, a PDP structure will now-be described.
FIG. 1 shows a partial perspective view of the PDP, and FIG. 2 schematically shows an electrode arrangement of the PDP.
As shown in FIG. 1, the PDP includes glass substrates 1 and 6 facing each other with a predetermined gap therebetween. Scan electrodes 4 and sustain electrodes 5 in pairs are formed in parallel on glass substrate 1, and scan electrodes 4 and sustain electrodes 5 are covered with dielectric layer 2 and protection film 3. A plurality of address electrodes 8 is formed on glass substrate 6, and address electrodes 8 are covered with insulator layer 7. Barrier ribs 9 are formed on insulator layer 7 between address electrodes 8, and phosphors 10 are formed on the surface of insulator layer 7 and between barrier ribs 9. Glass substrates 1 and 6 are provided facing each other with discharge spaces between glass substrates 1 and 6 so that scan electrodes 4 and sustain electrodes 5 can cross address electrodes 8. Discharge space 11 between address electrode 8 and a crossing part of a pair of scan electrode 4 and sustain electrode 5 forms discharge cell 12, which is schematically indicated.
As shown in FIG. 2, the electrodes of the PDP have an n×m matrix format. Address electrodes A1 to Am are arranged in the column (vertical) direction, and n scan electrodes Y1 to Yn and n sustain electrodes X1 to Xn are arranged in pairs in the row (horizontal) direction. Scan/sustain driving circuit 13 is coupled to scan electrodes Y1 to Yn and sustain electrodes X1 to Xn, and address driving circuit 15 is coupled to address electrodes A1 to Am.
In the general PDP, a frame is divided into a plurality of subfields and then driven, and gray scales are displayed by combination of the subfields. Each subfield includes a reset period, an address period, and a sustain period. In the reset period, wall charges formed by a previous sustain discharging are erased, and wall charges are set up so as to perform a next stable address discharging. In the address period, cells which are turned on and cells which are not turned on are selected, and the wall charges are accumulated on the turned-on cells (addressed cells). In the sustain period, a sustain discharging for displaying the actual image on the addressed cells is executed.
As shown in FIG. 3, the reset period includes a rising ramp period and a falling ramp period. In the rising ramp period, a ramp voltage gradually rises to voltage Vset from voltage Vs while address electrode A and sustain electrode X are maintained at 0V. While the ramp voltage rises, a weak reset discharging is generated to address electrode A and sustain electrode X from scan electrode Y in all the discharge cells. As a result, negative wall charges are accumulated on scan electrode Y, and positive wall charges are accumulated on address electrode A and sustain electrode X. More accurately, the wall charges are accumulated on protection film 3 which covers scan electrode Y and sustain electrode X and on insulator layer 7 which covers address electrode A. For ease of description, the wall charges are described to be accumulated on scan electrode Y, sustain electrode X, and address electrode A.
A ramp voltage which gradually falls to 0V from voltage Vs is applied to scan electrode Y while sustain electrode X is maintained at voltage Ve in the falling ramp period. While the ramp voltage falls, a weak reset discharging is generated in all the discharge cells. As a result, the negative wall charges on scan electrode Y are reduced, and the positive wall charges on sustain electrode X and address electrode A are reduced.
In this instance, it is required that a high voltage be applied to address electrode A for the address discharging during the address period since a large amount of charges are erased from among the positive wall charges accumulated on address electrode A according to the conventional waveform. That is, a switch having a high withstand voltage needs to be used by a circuit applying a voltage to address electrode A, and power consumption is also increased because of the high voltage.